· A minimum of Bachelor’s degree in Electrical Engineering or related field required, Master’s degree a plus
· 5-10 years experience in ASIC/FPGA verification.
· Expert skills in Verilog functional/power/performance verification and coverage analysis tehchniques
· Proficient in architecting and implementing verification environment.
· Solid understanding of System Verilog including latest verification methodologies VMM, UVM, OVM and assertion based test.
· In-depth knowledge and experience with Constrained-Random, Coverage Driven verification methodologies.
· Excellent written and verbal communication skills.
· Experience and knowledge of communication standards (802.3 Ethernet, 1588, OTN, Interlaken) highly desired.