* Strong foundation in layout design for analog/mixed-signal circuits in advanced CMOS processes.
* Extensive floorplanning, power grid and signal flow planning experience.
* Excellent understanding of signal and clock shielding and isolation techniques.
* Excellent understanding of process non-idealities such as STI stress, well proximity effect and design strategies to mitigate these effects.
* Experience in the layout of high-speed transceivers, PLLs, receivers, and transmitters
* Excellent written and oral communication skills are also required* Minimum education level/experience: Diploma + 10 yrs, BS + 8 yrs