Xilinx, Inc. (NASDAQ: XLNX) is the world’s leading provider of All Programmable technologies and devices, going beyond traditional programmable logic to enable both hardware and software programmability, integrate both digital and analog mixed-signal functions, and allow new levels of programmable interconnect in both monolithic and multi-die 3D ICs. The company’s products are coupled with a next-generation design environment and IP to service a broad range of customer needs, from programmable logic to programmable systems integration.
Xilinx chips are designed into automotive infotainment and driver safety, ultrasound imaging, robotically-assisted surgical systems, IT gear for wireless computing and mobile applications, consumer 3-D TVs, mobile communications used on the networked battlefield – and even sophisticated space vehicles exploring the outer reaches of the universe.
Develop and apply CAD software engineering methods, theories, and research techniques to support front-end and back-end digital/analog/mixed signal circuit design activities. Architect solutions to enable complete design environment for designs including third party IPs. Prepare design specifications, analysis, and solutions in the custom design environment including migrating design databases from CDBA to OpenAccess, migration SKILL functions, and providing PDK support. May specify materials, equipment, and supplies required for completion of projects and develop utilities to improve and enhance the productivity of circuit and layout designers. Additionally, the position will involve coding and testing of physical verification decks using the Calibre tool.
- BSEE or MSEE + 10 yrs experience
- Must be proficient in programming with SKILL and Perl languages
- Must be proficient with Virtuoso L/XL/GXL level
- Experience with coding Calibre based physical verification decks
- Good understanding of using and implementing design environment as well integration environment using third party PDK.
- Good understanding of building CAD environments requiring integration of third-party IP.
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