Candidates must have completed undergraduate studies in computer science or computer engineering focused on parallel programming models and parallel computing architectures. A completed Bachelor degree is expected.
Candidates must have implemented FPGA designs using Xilinx ISE and Xilinx EDK tools (or similar tools from other vendors) with a focus on constraints driven implementation (timing, floor plan, area). Candidates must have FPGA design simulation experience using HDL simulators and FPGA design debug experience with ChipScope. Candidates have implemented MicroBlaze systems and are intimately familiar with using interconnect IP to connect MicroBlaze to memory and I/O peripherals.
Candidates are experienced in processor micro architecture design and have implemented on an FPGA different processor architectures. Examples may include simple RISC processor, multi-threaded DSP processors, and packet classification micro engines.
Candidates have successful implemented HPC, wireless DSP, packet processing, and/or video processing applications using one or more parallel design environment (OpenCL, OpenMP, MPI, Mathworks and similar). Emphasis is placed on parallelizing for heterogeneous targets. Candidates have demonstrated experience evaluating and optimizing the compute performance of kernels and the associated communication overhead in multicore systems of the given applications.
Candidates are intimately familiar with embedded Linux and with user level vs kernel level driver development. Candidates have developed Linux hosted application libraries that program the different (multiple) computing and I/O resources of a given platform.
- Candidates have used FPGA HLS (high level synthesis) tools such as Vivado HLS.
- Candidates are familiar with the OpenCL specification and have written OpenCL applications for CPU/GPU or other target platforms.
- Candidates have programmed multicore CPU platforms using Intel TBB and similar threading packages.
- Candidates have programmed NVIDIA devices using CUDA.