|Job Title||Staff Design Verification Engineer|
|Location||Kanata, ON, CA|
Xilinx is looking for a talented individual to join the Ethernet and Interlaken Solutions Group (EISG) in the position of Design Verification Engineer. The successful candidate will be working as a contributing member of the verification team and will be responsible for the functional verification of state-of-the-art FPGA-based intellectual property used in the wired communication systems. It is expected that the candidate will be proficient in HDL behavioral and RTL coding, in scripting languages such as Perl and will master system/block level verification environment development using System Verilog and modern verification methodologies using coverage metric driven approach. It would also be desirable for applicants to have experience with wired communications protocols, FPGA architecture and design and EDA processes. The successful candidate will have a proven track record of delivering ASIC and/or FPGA solutions to the market having been involved in all stages of verification from development of verification strategies, environment implementation and coverage closure.
In addition to strong technical abilities, the position requires excellent written and verbal communication skills that will be utilized for cross-site collaboration, developing test plans and verification environment documentation.
Xilinx already holds a leading position in the wired infrastructure manufacturing industry and is technologically well positioned to drive the ‘programmable imperative’ into 400G and beyond advanced systems. This job opening presents an opportunity to work with best-in-class configurable silicon, software to develop IP products to help build the next generation global communication infrastructure.
· A minimum of Bachelor’s degree in Electrical Engineering or related field required, Master’s degree a plus
· 12+ years experience in ASIC/FPGA verification.
· Expert skills in Verilog functional/power/performance verification and coverage analysis tehchniques
· Proficient in architecting and implementing verification environment.
· Solid understanding of System Verilog including latest verification methodologies VMM, UVM, OVM and assertion based test.
· In-depth knowledge and experience with Constrained-Random, Coverage Driven verification methodologies.
· Excellent written and verbal communication skills.
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